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Extending ASSERT to HW/SW Co-design

Task 3 - Demonstration on a case study

A case study has been implemented to exercise the HW/SW co-design methodology from co-specification to co-synthesis phase.

This case study consist of a simplified space application for digital image processing.

Image Processing

There are two external entities interacting with the system: the Camera Simulator that provides images periodically and Ground which receives the images already processed. At the same time, Ground (stub simulating Ground) interacts with the OBSW sending telecommands and receiving telemetries.

Image Processing function is in charge of filtering the images received. It has three different filters implemented: high-pass, low-pass and vertical frequencies enhancement filters. But only one is active. The OBSW is in charge of managing this application.


Co-specification develops the System Model where both behavioural and structural information of the system are represented. Two different model viewpoints are defined:

  • System Logic View (Data Model, Interface and Functional Views): representation of the logic of control and algorithms, components, connections among components, etc. They are modelled with the ASSERT toolset (LabASSERT). Next figure depicts the Interface View:

  • InterfaceView

  • System Platform View: description of the hardware elements and the system platform architecture. It provides implementation details of the hardware elements: read time, word size, implementation technology, etc.

  • PlatformView


Evaluation of different partition schemes using the following tools:

  • AMT: generates the initial Partition View following a software centric approach. This view is manually modified to configure other partition solutions. For each partition scheme, AMT generates the ASSERT Concurrency View required by AADS-T.
  • AADS-T: provides the performance analysis results (e.g., use of CPU, power, etc) of the partition sheme selected.

All the partitions schemes are analysed and the one which provides better performance results and fulfils the project requirements is selected. The partition scheme selected is the following:

  • HW System: HW_Cotroller, Image_Processing, Image_Filter and Control.
  • SW System: OBSW and Stub_Simulating_Ground.

Then, hardware and software Data Models are generated from the common System Data Model. Hardware and software systems are implemented in two concurrent and integrated tracks.


Finally, HW and SW systems are synthesized. HW components are synthesized utilizing high-level synthesis and logic synthesis methodologies. SW synthesis implies generating from high-level specification the code for the processors that will be executing the SW part. This is automatically done by the ASSERT toolset. Additionally, communication synthesis is required to interface the hardware components and the processors.

Next image shows the HW/SW co-design use case: FPGA Virtex 5, Leon2 development board and the PC acting as camera simulator:

Image Processing